// Formal Verification Project
// Non-pipelined AES Unit

// Input selector

// 11/18/2011


module inputselector(data_in,
					 add_roundkey_o,
	 				 sub_bytes_o, 
					 shift_rows_o, 
					 mix_columns_o, 
					 state, 
					 sel);

input [1:0] sel;
input [0:127] data_in;
input [0:127] add_roundkey_o, sub_bytes_o, shift_rows_o, mix_columns_o;
output [0:127] state;

reg [0:127] temp_state;


always @* 
	begin
		case(sel)
			2'b00:	temp_state = add_roundkey_o;
			2'b01:	temp_state = sub_bytes_o;
			2'b10:	temp_state = shift_rows_o;
			2'b11:	temp_state = mix_columns_o;
			
			default: temp_state = data_in;
		endcase
	end // end always block

	assign state = temp_state;

endmodule